1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a voltage detection circuit and an internal voltage generator using the same.
2. Description of the Related Art
Generally, a semiconductor device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) includes an internal voltage generator. The semiconductor device may operate stably using internal voltages having various voltage levels generated from an internal voltage generator. There are generally two types of internal voltages. One is generated by down-converting a power supply voltage supplied from an external device, and another is generated by charge-pumping using the power supply voltage or a ground voltage. For example, in a DDR SDRAM, the former may be used as a core voltage and a precharge voltage. The latter may be used as a boosted voltage (e.g., an activation voltage for word lines) or a negative voltage (e.g., a substrate bias voltage for cell transistors).
As semiconductor devices are highly integrated, a design rule of a sub-micron level is applied to the design of an internal circuit, and a voltage level of a power supply voltage is lowered for a high speed. Thus, a design and a manner for generating a stable internal voltage using a low power supply voltage have been developed. Especially, since a circuit for generating a negative voltage has an influence on a minute noise of a power supply voltage, which is supplied from an exterior, a special attention is required in a design a circuit.
FIG. 1 is a block diagram illustrating a conventional internal voltage generator.
Referring to FIG. 1, a conventional internal voltage generator includes a reference voltage generating unit 110, a voltage detection unit 120, an oscillation unit 130, and a pumping unit 140.
The reference voltage generating unit 110 generates a reference voltage V_REF having a voltage level corresponding to an internal voltage V_INN. The voltage detection unit 120 compares a voltage level of the reference voltage V_REF with that of a feedback voltage V_FD and generates a detection signal DET based on a comparison result. That is, the voltage detection unit 120 generates the detection signal DET by detecting voltage level of the feedback voltage V_FD based on the voltage level of the reference voltage V_REF.
The oscillation unit 130 generates an oscillation signal OSC in response to the detection signal DET. The pumping unit 140 receives the oscillation signal OSC and generates an internal voltage V_INN by using a charge pumping operation. The internal voltage V_INN is fed back to the voltage detection unit 120.
FIG. 2 is a detailed diagram illustrating the reference voltage generating unit 110 and the voltage detection unit 120 shown in FIG. 1.
Referring to FIG. 2, the reference voltage generating unit 110 receives a source reference voltage V_SR and a bias voltage V_BS and generates the reference voltage V_REF. The voltage detection unit 120 compares the voltage level of the reference voltage V_REF with that of the feedback voltage V_FD and generates the detection signal DET based on a comparison result.
Meanwhile, a semiconductor device including a semiconductor memory device is required to perform a test operation (or a test mode) prior to commercialization, and the semiconductor device, which passes the test operation, is provided to a user.
The internal voltage generator shown in FIG. 1 may perform a test operation. A pad 210 receives an external reference voltage corresponding to the reference voltage V_REF during the test operation, and the voltage detection unit 120 uses the external reference voltage, which is received through the pad 210, as the reference voltage during the test operation.
Hereinafter, a test operation for the internal voltage generator will be described as below with reference to FIGS. 1 and 2.
The voltage detection unit 120 receives the external reference voltage through the pad 210 during a test operation. Herein, the external reference voltage has a voltage level corresponding to the reference voltage V_REF used in a normal operation (or a normal mode). The voltage detection unit 120 detects the feedback voltage V_FD using the external reference voltage. Then, the oscillation unit 130 generates the oscillation signal OSC in response to the detection signal DET. The pumping unit 140 generates the internal voltage V_INN in response to the oscillation signal OSC.
Generally, the internal voltage V_INN has a dispersion value, which is determined by a characteristic value of a unit circuit forming the voltage detection unit 120. Herein, a small dispersion value of the internal voltage V_INN represents that the internal voltage V_INN is stable. On the other hand, a large dispersion value of the internal voltage V_INN represents that the internal voltage V_INN is unstable. Thus, it may be preferable that the unit circuit forming the voltage detection unit 120 is designed to have the smallest dispersion value possible.
Referring to FIG. 2, when first resistors R1 and R11 of the voltage detection unit 120 are designed to have a high resistance, the dispersion value of the internal voltage V_INN becomes small. On the other hand, when first resistors R1 and R11 of the voltage detection unit 120 are designed to have a high resistance, some concerns occur as below. Here, the first resistors R1 and R11 are designed to have the same resistance.
In the test operation, since the external reference voltage inputted through the pad 210 may be increased to a level corresponding to a resistance of the first resistors R1 and R11, it may be possible to design the first resistors R1 and R11 having a high resistance. However, when the first resistors R1 and R11 have the high resistance, it may be impossible to perform a normal operation using a low power supply voltage. Thus, the first resistors R1 and R11 are designed to have a low resistance under the normal operation. However, this may cause the internal voltage V_INN to have a large dispersion value during the test operation, as described above.
Accordingly, a test result using the internal voltage V_INN may not be reliable since the dispersion value of the internal voltage is increased by the first resistors R1 and R11 having a low resistance.